© 1999 Fairchild Semiconductor Corporation DS009539 www.fairchildsemi.com
April 1988
Revised August 1999
7
4F27 T
r
ip
le
3-I
nput
NOR Gat
e
74F27
Triple 3-Input NOR Gate
General Description
This device contains three independent gates, each of
which performs the logic NOR function.

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Unit Loading/Fan Out
Connection Diagram
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Order Number Package Number Package Description
74F27SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F27SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F27PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description U.L. Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
A
n
, B
n
, C
n
Data Inputs 1.0/1.0 20 µA/−0.6 mA
O
n
Data Outputs 50/33.3 −1 mA/20 mA
Inputs Output
A
n
B
n
C
n
O
n
LLLH
XXH L
XHX
HX L