April 1988
Revised March 1999
7
4F192
U
p
/
D
own Deca
de Count
er
wit
h
Separ
ate
Up/
D
o
w
n
Cloc
ks
© 1999 Fairchild Semiconductor Corporation DS009496.prf www.fairchildsemi.com
74F192
Up/Down Decade Counter with Separate Up/Down
Clocks
General Description
The 74F192 is an up/down BCD decade (8421) counter.
Separate Count Up and Count Down Clocks are used, and
in either counting mode the circuits operate synchronously.
The outputs change state synchronously with the LOW-to-
HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down
outputs are used as the clocks for a subsequent stage
without extra logic, thus simplifying multistage counter
designs. Individual preset inputs allow the circuit to be used
as a programmable counter. Both the Parallel Load (PL)
and the Master Reset (MR) inputs asynchronously override
the clocks.
Features
a73 Guaranteed 4000V minimum ESD protection

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F192SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F192PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide