© 1999 Fairchild Semiconductor Corporation DS009475 www.fairchildsemi.com
April 1988
Revised July 1999
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74F125
Quad Buffer (3-STATE)
Features
a73 High impedance base inputs for reduced loading

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Unit Loading/Fan Out
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
Order Number Package Number Package Description
74F125SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F125PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
U.L. Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
A
n
, B
n
Inputs 1.0/0.033 20 µA/−20 µA
O
n
Outputs 600/106.6 (80) −12 mA/64 mA (48 mA)
Inputs Output
A
n
B
n
O
LLL
LHH
HXZ