© 1999 Fairchild Semiconductor Corporation DS011685 www.fairchildsemi.com
October 1994
Revised August 1999
7
4F1071 18-Bi
t Undersho
ot/
O
ve
rshoot

Cl
am
p
74F1071
18-Bit Undershoot/Overshoot Clamp
and ESD Protection Device
General Description
The 74F1071 is an 18-bit undershoot/overshoot clamp
which is designed to limit bus voltages and also to protect
more sensitive devices from electrical overstress due to
electrostatic discharge (ESD). The inputs of the device
aggressively clamp voltage excursions nominally at 0.5V
below and 7V above ground.
Features
a73 18-bit array structure in 20-pin package
a73 FAST Bipolar voltage clamping action
a73 Dual center pin grounds for min inductance
a73 Robust design for ESD protection
a73 Low input capacitance
a73 Optimum voltage clamping for 5V CMOS/TTL
applications

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Note: Simplified Component Representation
FAST is a registered trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74F1071SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F1071MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F1071MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide