C0083C0078C0055C0052C0067C0066C0084C0076C0086C0051C0050C0053C0049
C0076C0079C0087C0262C0086C0079C0076C0084C0065C0071C0069 C0049C0262C0079C0070C0262C0056 C0070C0069C0084 C0077C0085C0076C0084C0073C0080C0076C0069C0088C0069C0082C0047C0068C0069C0077C0085C0076C0084C0073C0080C0076C0069C0088C0069C0082
SCDS054I − MARCH 1998 − REVISED OCTOBER 2003
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C0068 5-Ω Switch Connection Between Two Ports
C0068 Rail-to-Rail Switching on Data I/O Ports
C0068 I
off
Supports Partial-Power-Down Mode
Operation
C0068 Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B4
B3
B2
B1
A
NC
OE
GND
V
CC
B5
B6
B7
B8
S0
S1
S2
D, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
RGY PACKAGE
(TOP VIEW)
116
89
2
3
4
5
6
7
15
14
13
12
11
10
B5
B6
B7
B8
S0
S1
B3
B2
B1
A
NC
OE
B4
S2
V
GND
CC
NC − No internal connection
description/ordering information
The SN74CBTLV3251 device is a 1-of-8 high-speed FET multiplexer/demultiplexer. The low on-state resistance
of the switch allows connections to be made with minimal propagation delay.
The select inputs (S0, S1, S2) control the data flow. The FET multiplexers/demultiplexers are disabled when
the output-enable (OE) input is high.
This device is fully specified for partial-power-down applications using I
off
. The I
off
feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Tape and reel SN74CBTLV3251RGYR CL251
SOIC − D
Tube SN74CBTLV3251D
CBTLV3251
−40°C to 85°C
Tape and reel SN74CBTLV3251DR
SSOP (QSOP) − DBQ Tape and reel SN74CBTLV3251DBQR CL251
TSSOP − PW Tape and reel SN74CBTLV3251PWR CL251
TVSOP − DGV Tape and reel SN74CBTLV3251DGVR CL251
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright  2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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