© 2002 Fairchild Semiconductor Corporation DS500631 www.fairchildsemi.com
October 2001
Revised February 2002
7
4
AL
VCH16373
Low
V
o
l
t
ag
e 16-
Bit
T
r
anspar
ent
Lat
c
h wi
th
Bushold
74ALVCH16373
Low Voltage 16-Bit Transparent Latch with Bushold
General Description
The ALVCH16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The ALVCH16373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH16373 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output compatibility up to 3.6V.
The 74ALVCH16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.65V to 3.6V V
CC
supply operation
a73 3.6V tolerant control inputs and outputs
a73 Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
a73 t
PD
(I
n
to O
n
)
3.6 ns max for 3.0V to 3.6V V
CC
4.5 ns max for 2.3V to 2.7V V
CC
6.8 ns max for 1.65V to 1.95V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 200V

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
Package
Number
Package Description
74ALVCH16373T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide