74ALVCH162374T
器件描述：Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26з Series Resistors in Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：94.19KB，共6页
Sponsor by e络盟器件资料摘要：
© 2002 Fairchild Semiconductor Corporation DS500628 www.fairchildsemi.com
September 2001
Revised February 2002
7
4
AL
VCH16237
4 Low
V
o
l
t
a
g
e 16-
Bit
D-
T
y
pe F
l
i
p
-Fl
op wi
th
Bushol
d
74ALVCH162374
Low Voltage 16-Bit D-Type Flip-Flop with Bushold
and 26Ω Series Resistors in Outputs
General Description
The ALVCH162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The ALVCH162374 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH162374 is also designed with 26Ω series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock drivers
and bus transceivers/transmitters.
The 74ALVCH162374 is designed for low voltage
(1.65V to 3.6V) V
CC
applications with output compatibility
up to 3.6V.
The 74ALVCH162374 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
a73 1.65V to 3.6V V
CC
supply operation
a73 3.6V tolerant control inputs and outputs
a73 Bushold data inputs eliminates the need for external
pull-up/pull-down resistors
a73 26Ω series resistors in outputs
a73 t
PD
(CLK to O
n
)
4.6 ns max for 3.0V to 3.6V V
CC
5.4 ns max for 2.3V to 2.7V V
CC
9.6 ns max for 1.65V to 1.95V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number
Package
Number
Package Descriptions
74ALVCH162374T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
CP
n
Clock Pulse Input
I
0
–I
15
Bushold Inputs
O
0
–O
15
Outputs
September 2001
Revised February 2002
7
4
AL
VCH16237
4 Low
V
o
l
t
a
g
e 16-
Bit
D-
T
y
pe F
l
i
p
-Fl
op wi
th
Bushol
d
74ALVCH162374
Low Voltage 16-Bit D-Type Flip-Flop with Bushold
and 26Ω Series Resistors in Outputs
General Description
The ALVCH162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The ALVCH162374 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH162374 is also designed with 26Ω series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock drivers
and bus transceivers/transmitters.
The 74ALVCH162374 is designed for low voltage
(1.65V to 3.6V) V
CC
applications with output compatibility
up to 3.6V.
The 74ALVCH162374 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
a73 1.65V to 3.6V V
CC
supply operation
a73 3.6V tolerant control inputs and outputs
a73 Bushold data inputs eliminates the need for external
pull-up/pull-down resistors
a73 26Ω series resistors in outputs
a73 t
PD
(CLK to O
n
)
4.6 ns max for 3.0V to 3.6V V
CC
5.4 ns max for 2.3V to 2.7V V
CC
9.6 ns max for 1.65V to 1.95V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number
Package
Number
Package Descriptions
74ALVCH162374T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
CP
n
Clock Pulse Input
I
0
–I
15
Bushold Inputs
O
0
–O
15
Outputs