74ALVCH162244
器件描述：Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26з Series Resistor in Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：81.15KB，共6页
Sponsor by e络盟器件资料摘要：
© 2002 Fairchild Semiconductor Corporation DS500632 www.fairchildsemi.com
September 2001
Revised February 2002
7
4
AL
VCH16224
4 Low
V
o
l
t
a
g
e 16-
Bit
Buf
f
e
r
/L
ine
Dri
ver
w
i
t
h
Bushol
d a
nd 26
Ω
Seri
es
Resi
st
or in Output
s
74ALVCH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26Ω Series Resistor in Outputs
General Description
The ALVCH162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level
The 74ALVCH162244 is also designed with 26Ω series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVCH162244 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output capability up to 3.6V.
The 74ALVCH162244 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
a73 1.65V to 3.6V V
CC
supply operation
a73 3.6V tolerant control inputs and outputs
a73 Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
a73 26Ω series resistors in outputs
a73 t
PD
4.2 ns max for 3.0V to 3.6V V
CC
4.9 ns max for 2.3V to 2.7V V
CC
7.6 ns max for 1.65V to 1.95V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number
Package
Number
Package Description
74ALVCH162244T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
I
0
–I
15
Bushold Inputs
O
0
–O
15
Outputs
September 2001
Revised February 2002
7
4
AL
VCH16224
4 Low
V
o
l
t
a
g
e 16-
Bit
Buf
f
e
r
/L
ine
Dri
ver
w
i
t
h
Bushol
d a
nd 26
Ω
Seri
es
Resi
st
or in Output
s
74ALVCH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26Ω Series Resistor in Outputs
General Description
The ALVCH162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level
The 74ALVCH162244 is also designed with 26Ω series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVCH162244 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output capability up to 3.6V.
The 74ALVCH162244 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
a73 1.65V to 3.6V V
CC
supply operation
a73 3.6V tolerant control inputs and outputs
a73 Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
a73 26Ω series resistors in outputs
a73 t
PD
4.2 ns max for 3.0V to 3.6V V
CC
4.9 ns max for 2.3V to 2.7V V
CC
7.6 ns max for 1.65V to 1.95V V
CC
a73 Uses patented noise/EMI reduction circuitry
a73 Latch-up conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number
Package
Number
Package Description
74ALVCH162244T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
I
0
–I
15
Bushold Inputs
O
0
–O
15
Outputs