74ALVC16841
器件描述：Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：95.78KB，共6页
Sponsor by e络盟器件资料摘要：
© 2001 Fairchild Semiconductor Corporation DS500690 www.fairchildsemi.com
November 2001
Revised November 2001
7
4
AL
VC1684
1
Low V
o
l
t
a
g
e
20-
Bit
T
r
anspar
ent Lat
c
h
wi
th 3.6V T
o
ler
a
nt
I
nputs and O
u
tput
s
74ALVC16841
Low Voltage 20-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The 74ALVC16841 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16841 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.65V–3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 t
PD
(D
n
to O
n
)
3.5 ns max for 3.0V to 3.6V V
CC
3.9 ns max for 2.3V to 2.7V V
CC
6.8 ns max for 1.65V to 1.95V V
CC
a73 Power-off high impedance inputs and outputs
a73 Supports live insertion and withdrawal (Note 1)
a73 Uses patented noise/EMI reduction circuitry
a73 Latchup conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number Package Number Package Description
74ALVC16841MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
LE
n
Latch Enable Input
D
0
–D
19
Inputs
O
0
–O
19
Outputs
November 2001
Revised November 2001
7
4
AL
VC1684
1
Low V
o
l
t
a
g
e
20-
Bit
T
r
anspar
ent Lat
c
h
wi
th 3.6V T
o
ler
a
nt
I
nputs and O
u
tput
s
74ALVC16841
Low Voltage 20-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The 74ALVC16841 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16841 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.65V–3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 t
PD
(D
n
to O
n
)
3.5 ns max for 3.0V to 3.6V V
CC
3.9 ns max for 2.3V to 2.7V V
CC
6.8 ns max for 1.65V to 1.95V V
CC
a73 Power-off high impedance inputs and outputs
a73 Supports live insertion and withdrawal (Note 1)
a73 Uses patented noise/EMI reduction circuitry
a73 Latchup conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number Package Number Package Description
74ALVC16841MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
LE
n
Latch Enable Input
D
0
–D
19
Inputs
O
0
–O
19
Outputs