© 2001 Fairchild Semiconductor Corporation DS500697 www.fairchildsemi.com
November 2001
Revised November 2001
7
4
AL
VC1682
7 Low
V
o
l
t
a
g
e 20-
Bit
Buf
f
e
r
/L
ine
Dri
ver
w
i
t
h
3.
6V T
o
l
e
rant

Input
s an
d Outp
uts
74ALVC16827
Low Voltage 20-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16827 contains twenty non-inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver carrying parity. The device is byte controlled. Each
byte has NOR output enables for maximum control flexibil-
ity.
The 74ALVC16827 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVC16827 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.65V to 3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 t
PD
3.0 ns max for 3.0V to 3.6V V
CC
3.5 ns max for 2.3V to 2.7V V
CC

6.0 ns max for 1.65V to 1.95V V
CC
a73 Power-off high impedance inputs and outputs
a73 Supports live insertion and withdrawal (Note 1)
a73 Uses patented noise/EMI reduction circuitry
a73 Latchup conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.

Ordering Code:
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number Package Number Package Description
74ALVC16827MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
I
0
–I
19
Inputs
O
0
–O
19
Outputs