74ALVC162827
器件描述：Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26з Series Resistors in the Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：77.43KB，共6页
Sponsor by e络盟器件资料摘要：
© 2001 Fairchild Semiconductor Corporation DS500698 www.fairchildsemi.com
November 2001
Revised November 2001
7
4
AL
VC1628
27
Low V
o
l
t
a
ge
20
-Bit
B
u
ff
er/
L
ine Dri
ver wit
h
3.
6V
T
o
l
e
ran
t
Input
s
a
nd
Out
puts and 26
Ω
Seri
es
Res
i
st
ors in the
O
u
tp
uts
74ALVC162827
Low Voltage 20-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in the Outputs
General Description
The ALVC162827 contains twenty non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is byte controlled. Each byte has NOR
output enables for maximum control flexibility.
The 74ALVC162827 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V. The
ALVC162827 is also designed with 26Ω resistors in the
outputs.
The 74ALVC162827 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.65V to 3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 26Ω series resistors in outputs
a73 t
PD
3.9 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
8.2 ns max for 1.65V to 1.95V V
CC
a73 Power-off high impedance inputs and outputs
a73 Supports live insertion and withdrawal (Note 1)
a73 Uses patented noise/EMI reduction circuitry
a73 Latchup conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number Package Number Package Description
74ALVC162827T MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
I
0
–I
19
Inputs
O
0
–O
19
Outputs
November 2001
Revised November 2001
7
4
AL
VC1628
27
Low V
o
l
t
a
ge
20
-Bit
B
u
ff
er/
L
ine Dri
ver wit
h
3.
6V
T
o
l
e
ran
t
Input
s
a
nd
Out
puts and 26
Ω
Seri
es
Res
i
st
ors in the
O
u
tp
uts
74ALVC162827
Low Voltage 20-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in the Outputs
General Description
The ALVC162827 contains twenty non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is byte controlled. Each byte has NOR
output enables for maximum control flexibility.
The 74ALVC162827 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V. The
ALVC162827 is also designed with 26Ω resistors in the
outputs.
The 74ALVC162827 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
a73 1.65V to 3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 26Ω series resistors in outputs
a73 t
PD
3.9 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
8.2 ns max for 1.65V to 1.95V V
CC
a73 Power-off high impedance inputs and outputs
a73 Supports live insertion and withdrawal (Note 1)
a73 Uses patented noise/EMI reduction circuitry
a73 Latchup conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number Package Number Package Description
74ALVC162827T MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
I
0
–I
19
Inputs
O
0
–O
19
Outputs