© 2001 Fairchild Semiconductor Corporation ds500720 www.fairchildsemi.com
December 2001
Revised December 2001
7
4
AL
VC132
Low V
o
l
t
age
Quad
2-I
nput
NAND Gate
wit
h

Schm
i
t
t
T
r
igg
e
r
Input
s a
nd 3.
6V T
o
l
e
rant

Input
s a
nd
Out
puts
74ALVC132
Low Voltage Quad 2-Input NAND Gate with
Schmitt Trigger Inputs and 3.6V Tolerant Inputs
and Outputs
General Description
The ALVC132 contains four 2-input NAND gates with
Schmitt Trigger Inputs. The pin configuration and function
are the same as the ALVC00 except the inputs have hys-
teresis between the positive-going and negative-going
input thresholds. This hysteresis is useful for transforming
slowly switching input signals into sharply defined, jitter-
free output signals. This product should be used where
noise margin greater than that of conventional gates is
required.
The ALVC132 is designed for low voltage (1.65V to 3.6V)
V
CC
applications with I/O compatibility up to 3.6V.
This product is fabricated with an advanced CMOS tech-
nology to achieve high-speed operation while maintaining
low CMOS power dissipation.
Features
a73 1.65V to 3.6V V
CC
supply operation
a73 3.6V tolerant inputs and outputs
a73 t
PD
3.8 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
8.2 ns max for 1.65V to 1.95V V
CC
a73 Power-off high impedance inputs and outputs
a73 Uses patented Quiet Series noise/EMI reduction
circuitry
a73 Latchup conforms to JEDEC JED78
a73 ESD performance:
Human body model > 2000V
Machine model > 250V

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Diagram
Pin Descriptions
Connection Diagram
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ALVC132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ALVC132MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Name Description
A
n
, B
n
Inputs
O
n
Outputs