74ACTQ652
器件描述：Quiet Series⑩ Transceiver/Register
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：104.48KB，共9页
Sponsor by e络盟器件资料摘要：
© 1999 Fairchild Semiconductor Corporation DS010933 www.fairchildsemi.com
June 1991
Revised November 1999
7
4
AC
TQ
652
Q
u
ie
t
Seri
es
T
r
anscei
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R
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s
ter
74ACTQ652
Quiet Series Transceiver/Register
General Description
The ACTQ652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to the
HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
The ACTQ652 utilizes Fairchild FACT Quiet Series tech-
nology to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to split ground bus for superior performance.
Features
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Guaranteed pin-to-pin skew AC performance
a73 Independent registers for A and B buses
a73 Multiplexed real-time and stored data
a73 Outputs source/sink 24 mA
a73 TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ652SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ652MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Pin Names Description
A
0
–A
7
, B
0
–B
7
A and B Inputs/3-STATE Outputs
CPAB, CPBA Clock Inputs
SAB, SBA Select Inputs
OEAB, OEBA Output Enable Inputs
June 1991
Revised November 1999
7
4
AC
TQ
652
Q
u
ie
t
Seri
es
T
r
anscei
ver/
R
egi
s
ter
74ACTQ652
Quiet Series Transceiver/Register
General Description
The ACTQ652 consists of bus transceiver circuits with D-
type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to the
HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
The ACTQ652 utilizes Fairchild FACT Quiet Series tech-
nology to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to split ground bus for superior performance.
Features
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Guaranteed pin-to-pin skew AC performance
a73 Independent registers for A and B buses
a73 Multiplexed real-time and stored data
a73 Outputs source/sink 24 mA
a73 TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ652SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ652MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Pin Names Description
A
0
–A
7
, B
0
–B
7
A and B Inputs/3-STATE Outputs
CPAB, CPBA Clock Inputs
SAB, SBA Select Inputs
OEAB, OEBA Output Enable Inputs