74ACTQ273
器件描述：Quiet Series Octal D-Type Flip-Flop
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：106.94KB，共9页
Sponsor by e络盟器件资料摘要：
© 1999 Fairchild Semiconductor Corporation DS010585 www.fairchildsemi.com
August 1989
Revised November 1999
7
4
AC
TQ
273
Q
u
ie
t Seri
es
O
c
t
a
l D-T
y
pe Fl
ip-
F
lop
74ACTQ273
Quiet Series Octal D-Type Flip-Flop
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) and Master Reset (MR) input load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
The ACTQ utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features
GTO output control and undershoot corrector in addition
to a split ground bus for superior performance.
Features
a73 I
CC
reduced by 50%
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Guaranteed pin-to-pin skew AC performance
a73 Improved latch-up immunity
a73 Buffered common clock and asynchronous master reset
a73 Outputs source/sink 24 mA
a73 4 kV minimum ESD immunity
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ273SC M20B 20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300” Wide Body
74ACTQ273SJ M20D 20-Lead Small Outline Package, EIAJ TYPE II, 5.3mm Wide
74ACTQ273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ273PC N20A 20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0
–D
7
Data Inputs
MR Master Reset
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs
August 1989
Revised November 1999
7
4
AC
TQ
273
Q
u
ie
t Seri
es
O
c
t
a
l D-T
y
pe Fl
ip-
F
lop
74ACTQ273
Quiet Series Octal D-Type Flip-Flop
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) and Master Reset (MR) input load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
The ACTQ utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features
GTO output control and undershoot corrector in addition
to a split ground bus for superior performance.
Features
a73 I
CC
reduced by 50%
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Guaranteed pin-to-pin skew AC performance
a73 Improved latch-up immunity
a73 Buffered common clock and asynchronous master reset
a73 Outputs source/sink 24 mA
a73 4 kV minimum ESD immunity
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ273SC M20B 20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300” Wide Body
74ACTQ273SJ M20D 20-Lead Small Outline Package, EIAJ TYPE II, 5.3mm Wide
74ACTQ273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ273PC N20A 20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0
–D
7
Data Inputs
MR Master Reset
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs