May 1991
Revised November 1998
7
4
A
C
TQ16240 16-
Bit

I
n
ve
r
t
ing Buff
er/
L
ine

Dri
ver wit
h

3
-
ST
A
T
E
Output
s
© 1999 Fairchild Semiconductor Corporation DS010924.prf www.fairchildsemi.com
74ACTQ16240
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16240 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ACTQ16240 utilizes Fairchild’s Quiet Series technol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control for superior performance.
Features
a73 Utilizes Fairchild’s FACT Quiet Series technology
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Guaranteed pin-to-pin output skew
a73 Separate control logic for each byte
a73 16-bit version of the ACTQ240
a73 Outputs source/sink 24 mA
a73 Additional specs for multiple output switching
a73 Output loading specs for both 50 pF and 250 pF loads

Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Pin Assignment
for SSOP and TSSOP
FACT, FACT Quiet Series, Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ16240SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Inputs (Active Low)
I
0
–I
15
Inputs
O
0
–O
15
Outputs