74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
April 1997
n HIGH SPEED:
fMAX = 250 MHz (TYP.) at VCC =5V
n LOW POWER DISSIPATION:
ICC =4µA (MAX.) at TA =25
o
C
n COMPATIBLE WITH TTL OUTPUTS
V
IH
=2V(MIN),V
IL
= 0.8V (MAX)
n 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
=24mA(MIN)
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT74 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C
2
MOS
technology.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
Schottky TTL.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74ACT74B 74ACT74M
M
(Micro Package)
B
(Plastic Package)
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