1/9July 2003
a73 HIGH SPEED: t
PD
= 4.8ns (TYP.) at V
CC
=5V
a73 LOW POWER DISSIPATION:
I
CC
=8µA(MAX.) at T
A
=25°C
a73 COMPATIBLE WITH TTL OUTPUTS
V
IH
=2V(MIN.),V
IL
= 0.8V (MAX.)
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
= 24mA (MIN) at V
CC
=4.5V
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
a73 FUNCTION COMPATIBLE WITH SERIES
16373 AND 16245 (244)
a73 IMPROVED LATCH-UP IMMUNITY
a73 IMPROVED ESD IMMUNITY
DESCRIPTION
The 74ACT16244 is a low voltage CMOS 16-BIT
D-TYPE LATCH and 16 BIT BUS TRANSCEIVER
with 3-STATE output non inverting fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
Both functions can be used as 16 bit or dual octal
devices, so the16 bit transceivercan beused ad 8
bit bus buffer plus 8 bit transceiver, or only 16 bit
buffer in select direction.
This device can be used to integrate in one chip
the internal logic component required to STV0701
to work ad P.O.D. interface in Digital TV
application. It is ideal for low power and high
speed 4.5 to 5.5. applications.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
74ACT32701
16-BIT D-TYPE LATCH PULS 16-BIT BUS BUFFER
WITH 3-STATE OUTPUTS (NON INVERTED)
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.
ORDER CODES
PACKAGE TRAY T & R
LFBGA96 74ACT32701LB 74ACT32701LBR
LFBGA96
(Top and Bottom view)
PRELIMINARY DATA
LOGIC DIAGRAM