EEWorld首页 新闻 论坛 博客 白皮书 专题 电子电路 电子器件 单片机 嵌入式 模拟电路 DSP FPGA 电源管理 手机/便携 医疗电子 汽车电子 工业控制
厂商索引:A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z

74ACT16373

器件描述:16-Bit Transparent Latch with 3-STATE Outputs
器件厂商:FAIRCHILD [Fairchild Semiconductor]
文件大小:90.95KB,共7页
Sponsor by e络盟
器件资料摘要:
© 1999 Fairchild Semiconductor Corporation DS500297 www.fairchildsemi.com
August 1999
Revised October 1999
7
4
AC
T1
6373
1
6
-Bi
t
T
r
anspa
rent

Lat
ch w
i
th 3-
ST
A
T
E O
u
t
put
s
74ACT16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACT16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is low, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state.
Features
a73 Separate control logic for each byte
a73 16-bit version of the ACT373
a73 Outputs source/sink 24 mA
a73 TTL-compatible inputs

Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACT16373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT16373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active Low)
LE
n
Latch Enable Input
I
0
–I
15
Inputs
O
0
–O
15
Outputs