16-Bit Transceivers
CY74FCT16245T
CY74FCT162245T
CY74FCT162H245T
SCCS026 - July 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
1CY74FCT16445T/2
H245T
Features
• FCT-E speed at 3.2 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of –40˚C to +85˚C
• V
CC
= 5V – 10%
CY74FCT16245T Features:
• 64 mA sink current, 32 mA source current
• Typical V
OLP
(ground bounce)<1.0V at V
CC
= 5V,
T
A
= 25˚C
CY74FCT162245T Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• Typical V
OLP
(ground bounce) <0.6V at V
CC
= 5V,
T
A
= 25˚C
CY74FCT162H245T Features:
• Bus hold on data inputs
• Eliminates the need for external pull-up or pull-down
resistors
Functional Description
These 16-bit transceivers are designed for use in bidirectional
synchronous communication between two buses, where high
speed and low power are required. With the exception of the
CY74FCT16245T, these devices can be operated either as
two independent octals or a single 16-bit transceiver. Direction
of data flow is controlled by (DIR), the Output Enable (OE)
transfers data when LOW and isolates the buses when HIGH.
The output buffers are designed with power off disable capa-
bility to allow for live insertion of boards.
The CY74FCT16245T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162245T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for mini-
mal undershoot and reduced ground bounce. The
CY74FCT162245T is ideal for driving transmission lines.
The CY74FCT162H245T is a 24-mA balanced output part that
has bus hold on the data inputs. The device retains the input’s
last state whenever the input goes to high impedance. This
eliminates the need for pull-up/down resistors and prevents
floating inputs.
GND
Logic Block Diagrams CY74FCT16245T,CY74FCT162245T,
CY74FCT162H245T
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
1
DIR
34
SSOP/TSSOP
Top View
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
1
B
1
1
B
2
1
B
3
1
B
4
1
A
1
1
A
2
1
A
3
1
A
4
1
OE
GND
GND
V
CC
1
B
7
1
B
8
1
B
5
1
B
6
1
A
5
1
A
6
1
A
7
1
A
8
V
CC
GND
GND
2
B
3
2
B
4
2
B
1
2
B
2
2
A
1
2
A
2
2
A
3
2
A
4
GND
GND
V
CC
2
B
7
2
B
8
2
B
5
2
B
6
2
A
5
2
A
6
2
A
7
2
A
8
V
CC
GND
2
DIR
2
OE
FCT16245–1
1
A
1
1
A
2
1
A
3
1
A
4
1
A
5
1
A
6
1
A
7
1
OE
1
B
1
1
B
2
1
B
3
1
B
4
1
B
5
1
B
6
1
B
7
1
DIR
1
A
8
1
B
8
FCT16245–2
2
A
1
2
A
2
2
A
3
2
A
4
2
A
5
2
A
6
2
A
7
2
OE
2
B
1
2
B
2
2
B
3
2
B
4
2
B
5
2
B
6
2
B
7
2
DIR
2
A
8
2
B
8
FCT16245–3
16245T
162245T
162H245T