74ACT1284
器件描述：IEEE 1284 Transceiver
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：226.55KB，共7页
Sponsor by e络盟器件资料摘要：
© 1999 Fairchild Semiconductor Corporation DS011683 www.fairchildsemi.com
June 1996
Revised November 1999
7
4
AC
T1
284 I
EEE 128
4 T
r
anscei
ver
74ACT1284
IEEE 1284 Transceiver
General Description
The 74ACT1284 contains four non-inverting bidirectional
buffers and three non-inverting buffers with open Drain out-
puts and high drive capability on the B Ports. It is intended
to provide a standard signaling method for a bi-direction
parallel peripheral in an Extended Capabilities Port mode
(ECP).
The HD (active HIGH) input pin enables the B Ports to
switch from open Drain to a high drive totem pole output,
capable of sourcing 14 mA on all seven buffers. The DIR
input determines the direction of data flow on the bidirec-
tional buffers. DIR (active HIGH) enables data flow from A
Ports to B Ports. DIR (active LOW) enables data flow from
B Ports to A Ports.
Features
a73 TTL-compatible inputs
a73 A Ports have standard 4 mA totem pole outputs
a73 Typical input hysteresis of 0.5V
a73 B Port high drive source/sink capability of 14 mA
a73 Bidirectional non-inverting buffers
a73 Supports IEEE P1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
a73 B Port outputs in High Impedance mode during power
down
a73 Guaranteed 4000V minimum ESD protection
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACT1284SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT1284MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ACT1284MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
HD High Drive Enable input (Active HIGH)
DIR Direction Control Input
A
1
- A
4
Side A Inputs or Outputs
B
1
- B
4
Side B Inputs or Outputs
A
5
- A
7
Side A Inputs
B
5
- B
7
Side B Outputs
June 1996
Revised November 1999
7
4
AC
T1
284 I
EEE 128
4 T
r
anscei
ver
74ACT1284
IEEE 1284 Transceiver
General Description
The 74ACT1284 contains four non-inverting bidirectional
buffers and three non-inverting buffers with open Drain out-
puts and high drive capability on the B Ports. It is intended
to provide a standard signaling method for a bi-direction
parallel peripheral in an Extended Capabilities Port mode
(ECP).
The HD (active HIGH) input pin enables the B Ports to
switch from open Drain to a high drive totem pole output,
capable of sourcing 14 mA on all seven buffers. The DIR
input determines the direction of data flow on the bidirec-
tional buffers. DIR (active HIGH) enables data flow from A
Ports to B Ports. DIR (active LOW) enables data flow from
B Ports to A Ports.
Features
a73 TTL-compatible inputs
a73 A Ports have standard 4 mA totem pole outputs
a73 Typical input hysteresis of 0.5V
a73 B Port high drive source/sink capability of 14 mA
a73 Bidirectional non-inverting buffers
a73 Supports IEEE P1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
a73 B Port outputs in High Impedance mode during power
down
a73 Guaranteed 4000V minimum ESD protection
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACT1284SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT1284MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ACT1284MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
HD High Drive Enable input (Active HIGH)
DIR Direction Control Input
A
1
- A
4
Side A Inputs or Outputs
B
1
- B
4
Side B Inputs or Outputs
A
5
- A
7
Side A Inputs
B
5
- B
7
Side B Outputs