74ACQ544
器件描述:Quiet Series⑩ Octal Registered Transceiver with 3-STATE Outputs
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器件资料摘要:
© 2000 Fairchild Semiconductor Corporation DS010685 www.fairchildsemi.com
March 1990
Revised September 2000
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74ACQ544 74ACTQ544
Quiet Series Octal Registered Transceiver
with 3-STATE Outputs
General Description
The ACQ/ACTQ544 is an inverting octal transceiver con-
taining two sets of D-type registers for temporary storage of
data flowing in either direction. Separate Latch Enable and
Output Enable inputs are provided for each register to per-
mit independent input and output control in either direction
of data flow. The 544 inverts data in both directions.
The ACQ/ACTQ utilizes Fairchild FACT Quiet Series
technology to guarantee quiet output switching and
improved dynamic threshold performance. FACT Quiet
Series features GTO output control and undershoot cor-
rector in addition to a split ground bus for superior perfor-
mance.
Features
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Guaranteed pin-to-pin skew AC performance
a73 8-bit inverting octal latched transceiver
a73 Separate controls for data flow in each direction
a73 Back-to-back registers for storage
a73 Outputs source/sink 24 mA
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACQ544SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ544SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ544SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ544SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
CEAB A-to-B Enable Input (Active LOW)
CEBA B-to-A Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input (Active LOW)
LEBA B-to-A Latch Enable Input (Active LOW)
A
0
–A
7
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
0
–B
7
B-to-A Data Inputs or
A-to-B 3-STATE Outputs