74ACQ543
器件描述：Quiet Series⑩ Octal Registered Transceiver with 3-STATE Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：93.4KB，共9页
Sponsor by e络盟器件资料摘要：
© 2000 Fairchild Semiconductor Corporation DS010154 www.fairchildsemi.com
January 1990
Revised August 2000
7
4
AC
Q543• 74ACTQ543 Q
u
i
e
t
Ser
i
es
Octal
Regi
st
ered T
r
ans
ceiver
wi
th 3-ST
A
T
E
Out
puts
74ACQ543 74ACTQ543
Quiet Series Octal Registered Transceiver
with 3-STATE Outputs
General Description
The ACQ/ACTQ543 is a non-inverting octal transceiver
containing two sets of D-type registers for temporary stor-
age of data flowing in either direction. Separate Latch
Enable and Output Enable inputs are provided for each
register to permit independent input and output control in
either direction of data flow.
The ACQ/ACTQ utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Guaranteed pin-to-pin skew AC performance
a73 8-bit octal latched transceiver
a73 Separate controls for data flow in each direction
a73 Back-to-back registers for storage
a73 Outputs source/sink 24 mA
a73 300 mil slim PDIP/SOIC
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.
Connection Diagram Pin Descriptions
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACQ543SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ543SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ543SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ543QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
74ACTQ543SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
CEAB A-to-B Enable Input (Active LOW)
CEBA B-to-A Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input (Active LOW)
LEBA B-to-A Latch Enable Input (Active LOW)
A
0
–A
7
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
0
–B
7
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
January 1990
Revised August 2000
7
4
AC
Q543• 74ACTQ543 Q
u
i
e
t
Ser
i
es
Octal
Regi
st
ered T
r
ans
ceiver
wi
th 3-ST
A
T
E
Out
puts
74ACQ543 74ACTQ543
Quiet Series Octal Registered Transceiver
with 3-STATE Outputs
General Description
The ACQ/ACTQ543 is a non-inverting octal transceiver
containing two sets of D-type registers for temporary stor-
age of data flowing in either direction. Separate Latch
Enable and Output Enable inputs are provided for each
register to permit independent input and output control in
either direction of data flow.
The ACQ/ACTQ utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Guaranteed pin-to-pin skew AC performance
a73 8-bit octal latched transceiver
a73 Separate controls for data flow in each direction
a73 Back-to-back registers for storage
a73 Outputs source/sink 24 mA
a73 300 mil slim PDIP/SOIC
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.
Connection Diagram Pin Descriptions
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACQ543SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ543SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ543SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ543QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
74ACTQ543SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
CEAB A-to-B Enable Input (Active LOW)
CEBA B-to-A Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input (Active LOW)
LEBA B-to-A Latch Enable Input (Active LOW)
A
0
–A
7
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
0
–B
7
B-to-A Data Inputs or
A-to-B 3-STATE Outputs