5-1
FACT DATA
C0068C0117C0097C0108 C0068C0262C0084C0121C0112C0101 C0080C0111C0115C0105C0116C0105C0118C0101
C0069C0100C0103C0101C0262C0084C0114C0105C0103C0103C0101C0114C0101C0100 C0070C0108C0105C0112C0262C0070C0108C0111C0112
The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear
and Set inputs and complementary (Q,Q) outputs. Information at the input is
transferred to the outputs on the positive edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q HIGH
• Outputs Source/Sink 24 mA
• ′ACT74 Has TTL Compatible Inputs
CP
1
C
D2
CP
2
1314 12 11 10 9 8
21 3 4 5 6 7
V
CC
C
D1
D
1
CP
1
S
D1
Q
1
Q
1
C
D2
D
2
CP
2
S
D2
Q
2
Q
2
C
D1
S
D1
Q
1
D
1
S
D2
Q
2
Q
2
D
2
GND
Q
1
PIN NAMES
D
1
, D
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs
C
D1
, C
D2
Direct Clear Inputs
S
D1
, S
D2
Direct Set Inputs
Q
1
, Q
1
, Q
2
, Q
2
Outputs
TRUTH TABLE (Each Half)
Inputs Outputs
S
D
C
D
CP D Q Q
L H X X H L
H L X X L H
L L X X H H
H H H H L
H H L L H
H H L X Q
0
Q
0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Q
0
(Q
0
) = Previous Q(Q) before
LOW-to-HIGH Transition of Clock
C0077C0067C0055C0052C0065C0067C0055C0052
C0077C0067C0055C0052C0065C0067C0084C0055C0052
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED
FLIP-FLOP
N SUFFIX
CASE 646-06
PLASTIC
D SUFFIX
CASE 751A-03
PLASTIC
LOGIC SYMBOL
S
D1
Q
1
CP
1
Q
1
C
D1
S
D2
Q
2
D
2
CP
2
Q
2
CD
2
D
1