74AC74
器件描述：DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
器件厂商：STMICROELECTRONICS [STMicroelectronics]
厂商主页：http://www.st.com/
文件大小：97.56KB，共11页
Sponsor by e络盟器件资料摘要：
74AC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
April 1997
n HIGH SPEED:
fMAX = 300 MHz (TYP.) at VCC =5V
n LOW POWER DISSIPATION:
ICC =4µA (MAX.) at TA =25
o
C
n HIGH NOISE IMMUNITY:
V
NIH
=V
NIL
= 28% V
CC
(MIN.)
n 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
=24mA(MIN)
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The AC74 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
Schottky TTL.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74AC74B 74AC74M
M
(Micro Package)
B
(Plastic Package)
1/11
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
April 1997
n HIGH SPEED:
fMAX = 300 MHz (TYP.) at VCC =5V
n LOW POWER DISSIPATION:
ICC =4µA (MAX.) at TA =25
o
C
n HIGH NOISE IMMUNITY:
V
NIH
=V
NIL
= 28% V
CC
(MIN.)
n 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
=24mA(MIN)
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The AC74 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
Schottky TTL.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74AC74B 74AC74M
M
(Micro Package)
B
(Plastic Package)
1/11