© 2000 Fairchild Semiconductor Corporation DS010133 www.fairchildsemi.com
November 1988
Revised August 2000
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74AC648
Octal Transceiver/Register with 3-STATE Outputs
General Description
The AC648 consists of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B
bus will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functions
available are illustrated in Figure 1, Figure 2, Figure 3, and
Figure 4.
Features
a73 Independent registers for A and B buses
a73 Multiplexed real-time and stored data transfers
a73 3-STATE outputs
a73 300 mil slim dual-in-line package
a73 Outputs source/sink 24 mA
a73 Inverted data to output

Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC648SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74AC648SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
A
0
–A
7
Data Register A Inputs,
Data Register A 3-STATE Outputs
B
0
– B
7
Data Register B Inputs,
Data Register B 3-STATE Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Transmit/Receive Inputs
DIR, G Output Enable Inputs