74AC273
器件描述：OCTAL D-TYPE FLIP FLOP WITH CLEAR
器件厂商：STMICROELECTRONICS [STMicroelectronics]
厂商主页：http://www.st.com/
文件大小：70.28KB，共10页
Sponsor by e络盟器件资料摘要：
74AC273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
PRELIMINARY DATA
November 1998
n HIGH SPEED:
fMAX = 190 MHz (TYP.) at VCC =5V
n LOW POWER DISSIPATION:
ICC =8 µA (MAX.) at TA =25
o
C
n HIGH NOISE IMMUNITY:
V
NIH
=V
NIL
=28%V
CC
(MIN.)
n 50Ω TRANSMISSIONLINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 24 mA (MIN)
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
VCC (OPR)= 2V to 6V
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The AC273 is a high-speed CMOS OCTAL
D-TYPE FLIP FLOP WITH CLEAR fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to equivalent Bipolar Schottky
TTL.
Information signals applied to D inputs are
transfered to the Q output on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentelyof the other inputs .
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
B
(Plastic Package)
ORDER CODES :
74AC273B 74AC273M
1/10
OCTAL D-TYPE FLIP FLOP WITH CLEAR
PRELIMINARY DATA
November 1998
n HIGH SPEED:
fMAX = 190 MHz (TYP.) at VCC =5V
n LOW POWER DISSIPATION:
ICC =8 µA (MAX.) at TA =25
o
C
n HIGH NOISE IMMUNITY:
V
NIH
=V
NIL
=28%V
CC
(MIN.)
n 50Ω TRANSMISSIONLINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 24 mA (MIN)
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
VCC (OPR)= 2V to 6V
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The AC273 is a high-speed CMOS OCTAL
D-TYPE FLIP FLOP WITH CLEAR fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to equivalent Bipolar Schottky
TTL.
Information signals applied to D inputs are
transfered to the Q output on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentelyof the other inputs .
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
B
(Plastic Package)
ORDER CODES :
74AC273B 74AC273M
1/10