74AC257
器件描述：Quad 2-Input Multiplexer with 3-STATE Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：97.71KB，共9页
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© 1999 Fairchild Semiconductor Corporation DS009949 www.fairchildsemi.com
November 1988
Revised November 1999
7
4
AC
2
57
• 74ACT257 Q
u
a
d
2-
Input
M
u
l
t
i
p
l
exer wit
h
3-
ST
A
T
E Output
s
74AC257 74ACT257
Quad 2-Input Multiplexer with 3-STATE Outputs
General Description
The AC/ACT257 is a quad 2-input multiplexer with 3-
STATE outputs. Four bits of data from two sources can be
selected using a Common Data Select input. The four out-
puts present the selected data in true (noninverted) form.
The outputs may be switched to a high impedance state by
placing a logic HIGH on the common Output Enable (OE)
input, allowing the outputs to interface directly with bus-ori-
ented systems.
Features
a73 I
CC
and I
OZ
reduced by 50%
a73 Multiplexer expansion by tying outputs together
a73 Noninverting 3-STATE outputs
a73 Outputs source/sink 24 mA
a73 ACT257 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC257SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC257SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC257MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC257PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT257SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT257SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT257MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT257PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
S Common Data Select Input
OE 3-STATE Output Enable Input
I
0a
–I
0d
Data Inputs from Source 0
I
1a
–I
1d
Data Inputs from Source 1
Z
a
–Z
d
3-STATE Multiplexer Outputs
November 1988
Revised November 1999
7
4
AC
2
57
• 74ACT257 Q
u
a
d
2-
Input
M
u
l
t
i
p
l
exer wit
h
3-
ST
A
T
E Output
s
74AC257 74ACT257
Quad 2-Input Multiplexer with 3-STATE Outputs
General Description
The AC/ACT257 is a quad 2-input multiplexer with 3-
STATE outputs. Four bits of data from two sources can be
selected using a Common Data Select input. The four out-
puts present the selected data in true (noninverted) form.
The outputs may be switched to a high impedance state by
placing a logic HIGH on the common Output Enable (OE)
input, allowing the outputs to interface directly with bus-ori-
ented systems.
Features
a73 I
CC
and I
OZ
reduced by 50%
a73 Multiplexer expansion by tying outputs together
a73 Noninverting 3-STATE outputs
a73 Outputs source/sink 24 mA
a73 ACT257 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC257SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC257SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC257MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC257PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT257SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT257SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT257MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT257PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
S Common Data Select Input
OE 3-STATE Output Enable Input
I
0a
–I
0d
Data Inputs from Source 0
I
1a
–I
1d
Data Inputs from Source 1
Z
a
–Z
d
3-STATE Multiplexer Outputs