5-1
FACT DATA
C0081C0117C0097C0100 C0068 C0070C0108C0105C0112C0262C0070C0108C0111C0112 C0087C0105C0116C0104
C0077C0097C0115C0116C0101C0114 C0082C0101C0115C0101C0116
The MC74AC/ACT175 is a high-speed quad D flip-flop. The device is useful for
general flip-flop requirements where clock and clear inputs are common. The
information on the D inputs is transferred to storage during the LOW-to-HIGH clock
transition. The device has a Master Reset to simultaneously clear all flip-flops, when
MR is low.
The MC74AC/ACT175 consists of four edge-triggered D flip-flops with individual
D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common
to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master
Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock
or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and
Master Reset are common to all storage elements.
• Outputs Source/Sink 24 mA
• ′ACT175 Has TTL Compatible Inputs
Pinout: 16-Lead Packages (Top View)
1516 14 13 12 11 10
21 3 4 5 6 7
V
CC
9
8
Q
3
Q
3
D
3
D
2
Q
2
Q
2
CP
MR Q
0
Q
0
D
0
D
1
Q
1
Q
1
GND
PIN NAMES
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
Outputs
D
0
– D
3
CP
MR
Q
0
– Q
3
Q
0
– Q
3
TRUTH TABLE
Inputs Outputs
MR CP D Qn Qn
L X X L H
H H H L
H L L H
H L X Qn Qn
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition of Clock
C0077C0067C0055C0052C0065C0067C0049C0055C0053
C0077C0067C0055C0052C0065C0067C0084C0049C0055C0053
QUAD D FLIP-FLOP
WITH MASTER RESET
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
D
0
D
1
D
2
D
3
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
CP
MR