74AC161
器件描述：Synchronous Presettable Binary Counter
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：115.8KB，共11页
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© 1999 Fairchild Semiconductor Corporation DS009931 www.fairchildsemi.com
November 1988
Revised November 1999
7
4
AC
1
61 •
74ACT161
Synchronous
Pre
sett
a
ble
Bi
nary
Counter
74AC161 74ACT161
Synchronous Presettable Binary Counter
General Description
The AC/ACT161 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for
application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multistage counters. The
AC/ACT161 has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW.
Features
a73 I
CC
reduced by 50%
a73 Synchronous counting and loading
a73 High-speed synchronous expansion
a73 Typical count rate of 125 MHz
a73 Outputs source/sink 24 mA
a73 ACT161 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC161SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC161PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT161SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT161PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
MR
Asynchronous Master Reset Input
P
0
–P
3
Parallel Data Inputs
PE
Parallel Enable Inputs
Q
0
–Q
3
Flip-Flop Outputs
TC Terminal Count Output
November 1988
Revised November 1999
7
4
AC
1
61 •
74ACT161
Synchronous
Pre
sett
a
ble
Bi
nary
Counter
74AC161 74ACT161
Synchronous Presettable Binary Counter
General Description
The AC/ACT161 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for
application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multistage counters. The
AC/ACT161 has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW.
Features
a73 I
CC
reduced by 50%
a73 Synchronous counting and loading
a73 High-speed synchronous expansion
a73 Typical count rate of 125 MHz
a73 Outputs source/sink 24 mA
a73 ACT161 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC161SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC161PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT161SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT161PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
MR
Asynchronous Master Reset Input
P
0
–P
3
Parallel Data Inputs
PE
Parallel Enable Inputs
Q
0
–Q
3
Flip-Flop Outputs
TC Terminal Count Output