November 1992
Revised January 1999
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© 1999 Fairchild Semiconductor Corporation DS011512.prf www.fairchildsemi.com
74ABT652
Octal Transceivers and Registers with 3-STATE Outputs
General Description
The ABT652 consists of bus transceiver circuits with D-
type flip-flops and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to HIGH
logic level. Output Enable pins (OEAB, OEBA) are pro-
vided to control the transceiver function.
Features
a73 Independent registers for A and B buses
a73 Multiplexed real-time and stored data
a73 A and B output sink capability of 64 mA, source
capability of 32 mA
a73 Guaranteed output skew
a73 Guaranteed multiple output switching specifications
a73 Output switching specified for both 50 pF and
250 pF loads
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance
a73 Guaranteed latchup protection
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Nondestructive hot insertion capability

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for
SOIC, SSOP and TSSOP
Pin Descriptions
Order Number Package Number Package Description
74ABT652CSC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT652CMSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT652CMTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
A
0
–A
7
Data Register A Inputs/3-STATE Outputs
B
0
–B
7
Data Register B Inputs/3-STATE Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Select Inputs
OEAB, OEBA Output Enable Inputs