74ABT377
器件描述：Octal D-Type Flip-Flop with Clock Enable
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：101.67KB，共9页
Sponsor by e络盟器件资料摘要：
© 1999 Fairchild Semiconductor Corporation DS011550 www.fairchildsemi.com
January 1993
Revised November 1999
7
4
AB
T3
77
Oct
a
l D-T
y
pe Fl
ip-
F
lop wit
h
Cl
ock Enable
74ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ABT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
a73 Clock enable for address and data synchronization
applications
a73 Eight edge-triggered D-type flip-flops
a73 Buffered common clock
a73 See ABT273 for master reset version
a73 See ABT373 for transparent latch version
a73 See ABT374 for 3-STATE version
a73 Output sink capability of 64 mA, source capability
of 32 mA
a73 Guaranteed latchup protection
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Non-destructive hot insertion capability
a73 Disable time less than enable time to avoid bus
contention
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Truth Table
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial c17 = LOW-to-HIGH Clock Transition
h = HIGH Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
I = LOW Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
Order Number Package Number Package Description
74ABT377CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT377CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT377CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT377CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Descriptions
D
0
–D
7
Data Inputs
CE
Clock Enable (Active LOW)
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs
Operating Mode Inputs Output
CP CE D
n
Q
n
Load “1” c17 Ih H
Load “0” c17 II L
Hold c17 h X No Change
(Do Nothing) X H X No Change
January 1993
Revised November 1999
7
4
AB
T3
77
Oct
a
l D-T
y
pe Fl
ip-
F
lop wit
h
Cl
ock Enable
74ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ABT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
a73 Clock enable for address and data synchronization
applications
a73 Eight edge-triggered D-type flip-flops
a73 Buffered common clock
a73 See ABT273 for master reset version
a73 See ABT373 for transparent latch version
a73 See ABT374 for 3-STATE version
a73 Output sink capability of 64 mA, source capability
of 32 mA
a73 Guaranteed latchup protection
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Non-destructive hot insertion capability
a73 Disable time less than enable time to avoid bus
contention
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Truth Table
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial c17 = LOW-to-HIGH Clock Transition
h = HIGH Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
I = LOW Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
Order Number Package Number Package Description
74ABT377CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT377CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT377CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT377CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Descriptions
D
0
–D
7
Data Inputs
CE
Clock Enable (Active LOW)
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs
Operating Mode Inputs Output
CP CE D
n
Q
n
Load “1” c17 Ih H
Load “0” c17 II L
Hold c17 h X No Change
(Do Nothing) X H X No Change