74ABT273
器件资料摘要：
© 1999 Fairchild Semiconductor Corporation DS011549 www.fairchildsemi.com
January 1993
Revised November 1999
7
4
AB
T2
73
Oct
a
l D-T
y
pe Fl
ip-
F
lop
74ABT273
Octal D-Type Flip-Flop
General Description
The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
a73 Eight edge-triggered D-type flip-flops
a73 Buffered common clock
a73 Buffered, asynchronous Master Reset
a73 See ABT377 for clock enable version
a73 See ABT373 for transparent latch version
a73 See ABT374 for 3-STATE version
a73 Output sink capability of 64 mA, source capability of
32 mA
a73 Guaranteed latchup protection
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Non-destructive hot insertion capability
a73 Disable time less than enable time to avoid bus conten-
tion
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Order Number Package Number Package Description
74ABT273CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT273CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
D
0
–D
7
Data Inputs
MR Master Reset (Active LOW)
CP Clock Pulse Input (Active Rising Edge)
Q
0
–Q
7
Data Outputs
January 1993
Revised November 1999
7
4
AB
T2
73
Oct
a
l D-T
y
pe Fl
ip-
F
lop
74ABT273
Octal D-Type Flip-Flop
General Description
The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
a73 Eight edge-triggered D-type flip-flops
a73 Buffered common clock
a73 Buffered, asynchronous Master Reset
a73 See ABT377 for clock enable version
a73 See ABT373 for transparent latch version
a73 See ABT374 for 3-STATE version
a73 Output sink capability of 64 mA, source capability of
32 mA
a73 Guaranteed latchup protection
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Non-destructive hot insertion capability
a73 Disable time less than enable time to avoid bus conten-
tion
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Order Number Package Number Package Description
74ABT273CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT273CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
D
0
–D
7
Data Inputs
MR Master Reset (Active LOW)
CP Clock Pulse Input (Active Rising Edge)
Q
0
–Q
7
Data Outputs