74ABT16646
器件描述：16-Bit Transceivers and Registers with 3-STATE Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：84.06KB，共9页
Sponsor by e络盟器件资料摘要：
© 1999 Fairchild Semiconductor Corporation DS011644 www.fairchildsemi.com
October 1993
Revised November 1999
7
4
AB
T1
6646 1
6
-Bi
t
T
r
ansc
eiver
s an
d Regi
ster
s wi
th
3-
S
T
A
T
E Out
puts
74ABT16646
16-Bit Transceivers and Registers with 3-STATE Outputs
General Description
The ABT16646 consists of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is Active
LOW. In the isolation mode (control OE HIGH), A data may
be stored in the B register and/or B data may be stored in
the A register.
Features
a73 Independent registers for A and B buses
a73 Multiplexed real-time and stored data
a73 A and B output sink capability of 64 mA, source
capability of 32 mA
a73 Guaranteed latchup protection
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Nondestructive hot insertion capability
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Order Number Package Number Package Description
74ABT16646CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16646CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
A
0
–A
15
Data Register A Inputs/
3-STATE Outputs
B
0
–B
15
Data Register B Inputs/
3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
SAB
n
, SBA
n
Select Inputs
OE
n
Output Enable Input
DIR Direction Control Input
October 1993
Revised November 1999
7
4
AB
T1
6646 1
6
-Bi
t
T
r
ansc
eiver
s an
d Regi
ster
s wi
th
3-
S
T
A
T
E Out
puts
74ABT16646
16-Bit Transceivers and Registers with 3-STATE Outputs
General Description
The ABT16646 consists of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is Active
LOW. In the isolation mode (control OE HIGH), A data may
be stored in the B register and/or B data may be stored in
the A register.
Features
a73 Independent registers for A and B buses
a73 Multiplexed real-time and stored data
a73 A and B output sink capability of 64 mA, source
capability of 32 mA
a73 Guaranteed latchup protection
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Nondestructive hot insertion capability
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Order Number Package Number Package Description
74ABT16646CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16646CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
A
0
–A
15
Data Register A Inputs/
3-STATE Outputs
B
0
–B
15
Data Register B Inputs/
3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
SAB
n
, SBA
n
Select Inputs
OE
n
Output Enable Input
DIR Direction Control Input