© 2000 Fairchild Semiconductor Corporation DS006516 www.fairchildsemi.com
August 1986
Revised February 2000
DM7442A
BCD t
o
Deci
m
a
l
Decoder
DM7442A
BCD to Decimal Decoder
General Description
These BCD-to-decimal decoders consist of eight inverters
and ten, four-input NAND gates. The inverters are con-
nected in pairs to make BCD input data available for
decoding by the NAND gates. Full decoding of input logic
ensures that all outputs remain off for all invalid (10–15)
input conditions.
Features
a73 Diode clamped inputs
a73 Also for application as 4-line-to-16-line decoders;
3-line-to-8-line decoders
a73 All outputs are high for invalid input conditions
a73 Typical power dissipation 140 mW
a73 Typical propagation delay 17 ns

Ordering Code:
Connection Diagram
Order Number Package Number Package Description
DM7442AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide