September 1983
Revised February 1999
MM74HC273 O
c
tal

D-
T
ype Fl
ip-
F
lops

wit
h
C
l
ear
© 1999 Fairchild Semiconductor Corporation DS005331.prf www.fairchildsemi.com
MM74HC273
Octal D-Type Flip-Flops with Clear
General Description
The MM74HC273 edge triggered flip-flops utilize advanced
silicon-gate CMOS technology to implement D-type flip-
flops. They possess high noise immunity, low power, and
speeds comparable to low power Schottky TTL circuits.
This device contains 8 master-slave flip-flops with a com-
mon clock and common clear. Data on the D input having
the specified setup and hold times is transferred to the Q
output on the LOW-to-HIGH transition of the CLOCK input.
The CLEAR input when LOW, sets all outputs to a low
state.
Each output can drive 10 low power Schottky TTL equiva-
lent loads. The MM74HC273 is functionally as well as pin
compatible to the 74LS273. All inputs are protected from
damage due to static discharge by diodes to V
CC
and
ground.
Features
a73 Typical propagation delay: 18 ns
a73 Wide operating voltage range
a73 Low input current: 1 µA maximum
a73 Low quiescent current: 80 µA (74 Series)
a73 Output drive: 10 LS-TTL loads

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Order Number Package Number Package Description
MM74HC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 0.300” Wide
MM74HC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC273MTC MTC20 20-Lead thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide