M54HC194
M74HC194
October 1992
4 BIT PIPO SHIFT REGISTER
B1R
(Plastic Package)
ORDER CODES :
M54HC194F1R M74HC194M1R
M74HC194B1R M74HC194C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
DESCRIPTION
.HIGH SPEED
tPD = 12 ns (TYP.) AT VCC =5V
.LOW POWER DISSIPATION
I
CC
=4µA (MAX.) AT T
A
=25°C
.OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.SYMMETRICAL OUTPUT IMPEDANCE
IOH =I
OL
= 4 mA (MIN.)
.BALANCED PROPAGATION DELAYS
tPLH =tPHL
.HIGH NOISE IMMUNITY
V
NIH
=V
NIL
=28%V
CC
(MIN.)
.WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
.PIN AND FUNCTION COMPATIBLE
WITH 54/74LS194
TheM54/74HC194 isahigh speed CMOS4BITPIPO
SHIFT REGISTER fabricated in silicon gate C
2
MOS
technology. It has the same high speed performance
of LSTTL combined with true CMOS low power con-
sumption. This SHIFT REGISTER is designed to in-
corporate virtually allof thefeaturesasystemdesigner
may want in a shift register. It features parallel inputs,
parallel outputs, right shift and left shift serial inputs,
clear line. The register has four distinct modes ofoper-
ation : PARALLEL (broadside) LOAD ; SHIFT RIGHT
(in the direction Q
A
Q
D
); SHIFT LEFT ; INHIBIT
CLOCK (do nothing). Synchronous parallel loading is
accomplished byapplying thefour databitsand taking
both mode control inputs, S0 and S1 high. The data
are loaded into their respective flip-flops and appear
at the outputs after the positive transition of the
CLOCK input. During loading, serial data flow is in-
hibited.Shift right is accomplished synchronously with
the rising edge of the clock pulse when S0 is high and
S1 is low. Serial data for this mode is entered at the
SHIFT RIGHT data input. When S0 is low and S1 is
high,data shiftsleft synchronously and new datais en-
tered at the SHIFT LEFT serial input. Clocking of the
flipflops isinhibited when bothmode control inputs are
low. The mode control inputs should be changed only
when theCLOCKinput ishigh. All inputs areequipped
with protection circuits against static discharge and
transient excess voltage.
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