C0077C0079C0084C0079C0082C0079C0076C0065
SEMICONDUCTOR TECHNICAL DATA
1 REV 6 Motorola, Inc. 1995
10/95
C0081C0117C0097C0100 C0051C0045C0083C0116C0097C0116C0101 C0068 C0070C0108C0105C0112C0045C0070C0108C0111C0112 C0119C0105C0116C0104
C0067C0111C0109C0109C0111C0110 C0067C0108C0111C0099C0107 C0097C0110C0100 C0082C0101C0115C0101C0116
High–Performance Silicon–Gate CMOS
The MC74HC173 is identical in pinout to the LS173. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Data, when enabled, are clocked into the four D flip–flops with the rising
edge of the common Clock. When either or both of the Output Enable
Controls is high, the outputs are in a high–impedance state. This feature
allows the HC173 to be used in bus–oriented systems. The Reset feature is
asynchronous and active high.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity 208 FETs or 52 Equivalent Gates
FUNCTION TABLE
Inputs Output
Output Enables
Reset Clock
Data Enables
Data
DOE1 OE2 DE1 DE2 Q
L L H X X X X L
L L L L X X X No Change
L L L H X X X No Change
L L L H X X No Change
L L L X H X No Change
L L L L L L L
L L L L L H H
L L L X X X No Change
L H X X X X X High Impedance
H L X X X X X High Impedance
H H X X X X X High Impedance
C0077C0067C0055C0052C0072C0067C0049C0055C0051
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
D2
D1
D0
RESET
V
CC
DE1
DE2
D3
Q1
Q0
OE2
OE1
GND
CLOCK
Q3
Q2
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
1
16
1
16
LOGIC DIAGRAM
V
CC
= PIN 16
GND = PIN 8
DATA
INPUTS
3–STATE
NONINVERTING
OUTPUTS
D0
D1
D2
D3
14
13
12
11
3
4
5
6
Q0
Q1
Q2
Q3
CLOCK
7
DATA–
ENABLES
OUTPUT
ENABLES
DE1
DE2
OE1
OE2
RESET
9
10
15
1
2