5-372
FAST AND LS TTL DATA
4-STAGE PRESETTABLE
RIPPLE COUNTERS
The SN54/74LS196 decade counter is partitioned into divide-by-two and di-
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)
sequence or in a bi-quinary mode producing a 50% duty cycle output. The
SN54/74LS197 contains divide-by-two and divide-by-eight sections which
can be combined to form a modulo-16 binary counter. Low Power Schottky
technology is used to achieve typical count rates of 70 MHz and power dis-
sipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)
overrides clocked operations and asynchronously loads the data on the Par-
allel Data inputs (P
n
) into the flip-flops. This preset feature makes the circuits
usable as programmable counters. The circuits can also be used as 4-bit
latches, loading data from the Parallel Data inputs when PL is LOW and stor-
ing the data when PL is HIGH.
• Low Power Consumption — Typically 80 mW
• High Counting Rates — Typically 70 MHz
• Choice of Counting Modes — BCD, Bi-Quinary, Binary
• Asynchronous Presettable
• Asynchronous Master Reset
• Easy Multistage Cascading
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
C0049C0052 C0049C0051 C0049C0050 C0049C0049 C0049C0048 C0057
C0049 C0050 C0051 C0052 C0053 C0054
C0056
C0055
C0086
C0067C0067
C0077C0082 C0081
C0051
C0080
C0051
C0080
C0049
C0081
C0049
C0067C0080
C0048
C0080C0076 C0081
C0050
C0080
C0050
C0080
C0048
C0081
C0048
C0067C0080
C0049
C0071C0078C0068
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES LOADING (Note a)
HIGH LOW
CP
0
Clock (Active LOW Going Edge) 1.0 U.L. 1.5 U.L.
Input to Divide-by-Two Section
CP
1
(LS196) Clock (Active LOW Going Edge) 2.0 U.L. 1.75 U.L.
Input to Divide-by-Five Section
CP
1
(LS197) Clock (Active LOW Going Edge) 1.0 U.L. 0.8 U.L.
Input to Divide-by-Eight Section
MR Master Reset (Active LOW) Input 1.0 U.L. 0.5 U.L.
PL Parallel Load (Active LOW) Input 0.5 U.L. 0.25 U.L.
P
0
–P
3
Data Inputs 0.5 U.L. 0.25 U.L.
Q
0
–Q
3
Outputs (Notes b, c) 10 U.L. 5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
c. In addition to loading shown, Q
0
can also drive CP
1
.
SN54/74LS196
SN54/74LS197
4-STAGE PRESETTABLE
RIPPLE COUNTERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
14
1
D SUFFIX
SOIC
CASE 751A-02
LOGIC SYMBOL
C0067C0080
C0048
C0067C0080
C0049
C0080C0076
C0077C0082
C0080
C0048
C0081
C0048
C0080
C0049
C0080
C0050
C0080
C0051
C0081
C0049
C0081
C0050
C0081
C0051
C0049 C0052 C0049C0048 C0051 C0049C0049
C0049C0050C0050C0057C0053C0049C0051
C0054
C0056
C0086
C0067C0067
C0061 C0080C0073C0078 C0049C0052
C0071C0078C0068 C0061 C0080C0073C0078 C0055