TL/F/9588
54F/74F676
16-Bit
Serial/Parallel-In,
Serial-Out
Shift
Register
December 1994
54F/74F676
16-Bit Serial/Parallel-In, Serial-Out Shift Register
General Description
The ’F676 contains 16 flip-flops with provision for synchro-
nous parallel or serial entry and serial output. When the
Mode (M) input is HIGH, information present on the parallel
data (P
0
–P
15
) inputs is entered on the falling edge of the
Clock Pulse (CP) input signal. When M is LOW, data is shift-
ed out of the most significant bit position while information
present on the Serial (SI) input shifts into the least signifi-
cant bit position. A HIGH signal on the Chip Select (CS)
input prevents both parallel and serial operations.
Features
Y
16-bit parallel-to-serial conversion
Y
16-bit serial-in, serial-out
Y
Chip select control
Y
Slim 24 lead 300 mil package
Commercial Military
Package
Package Description
Number
74F676PC N24A 24-Lead (0.600 Wide) Molded Dual-In-Line
74F676SPC N24C 24-Lead (0.300 Wide) Molded Dual-In-Line
54F676DM (Note 2) J24A 24-Lead (0.600 Wide) Ceramic Dual-In-Line
54F676SDM (Note 2) J24F 24-Lead (0.300 Wide) Ceramic Dual-In-Line
74F676SC (Note 1) M24B 24-Lead (0.300 Wide) Molded Small Outline, JEDEC
54F676FM (Note 2) W24C 24-Lead Cerpack
54F676LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13 reel. Use suffix e SCX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB.
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
TL/F/9588–2
Pin Assignment
for LCC
TL/F/9588–3
TRI-STATE is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.