54ACT112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The ’ACT112 contains two independent, high-speed JK
flip-flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trigger-
ing occurs at a voltage level of the clock and is not directly
related to the transition time. The J and K inputs can change
when the clock is in either state without affecting the flip-flop,
provided that they are in the desired state during the recom-
mended setup and hold times relative to the falling edge of
the clock. A LOW signal on S
D
or C
D
prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW sig-
nals on S
D
and C
D
force both Q and Q HIGH.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
n ’ACT112 has TTL-compatible inputs
n Outputs source/sink 24 mA
n Standard Microcircuit Drawing (SMD) 5962-8995001
Connection Diagram Pin Descriptions
Pin Names Description
J
1
,J
2
,K
1
,K
2
Data Inputs
CP
1
,CP
2
Clock Pulse Inputs
(Active Falling Edge)
C
D1
,C
D2
Direct Clear Inputs (Active LOW)
S
D1
,S
D2
Direct Set Inputs (Active LOW)
Q
1
,Q
2
,Q
1
,Q
2
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
Pin Assigment for
DIP and Flatpack
DS100976-3
Pin Assigment
for LCC
DS100976-5
September 1998
54ACT1
12
Dual
JK
Negative
Edge-T
riggered
Flip-Flop
© 1998 National Semiconductor Corporation DS100976 www.national.com