54AC74 • 54ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs. In-
formation at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to
the transition time of the positive-going pulse. After the Clock
Pulse input threshold voltage has been passed, the Data in-
put is locked out and information present will not be trans-
ferred to the outputs until the next rising edge of the Clock
Pulse input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
n I
CC
reduced by 50%
n Output source/sink 24 mA
n ’ACT74 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC74: 5962-88520
— ’ACT74: 5962-87525
Logic Symbols
Pin Names Description
D
1
,D
2
Data Inputs
CP
1
,CP
2
Clock Pulse Inputs
C
D1
,C
D2
Direct Clear Inputs
S
D1
,S
D2
Direct Set Inputs
Q
1
,Q
1
,Q
2
,Q
2
Outputs
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
DS100266-1
IEEE/IEC
DS100266-3
DS100266-2
August 1998
54AC74
•
54ACT74
Dual
D-T
ype
Positive
Edge-T
riggered
Flip-Flop
© 1998 National Semiconductor Corporation DS100266 www.national.com