54AC109 • 54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT109 consists of two high-speed completely in-
dependent transition clocked JK flip-flops. The clocking op-
eration is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop
(refer to ’AC/’ACT74 data sheet) by connecting the J and K
inputs together.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
n I
CC
reduced by 50%
n Outputs source/sink 24 mA
n ’ACT109 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC109: 5962-89551
— ’ACT109: 5962-88534
Logic Symbol
Pin Names Description
J
1
,J
2
,K
1
,K
2
Data Inputs
CP
1
,CP
2
Clock Pulse Inputs
C
D1
,C
D2
Direct Clear Inputs
S
D1
,S
D2
Direct Set Inputs
Q
1
,Q
2
,Q
1
,Q
2
Outputs
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
DS100267-1
DS100267-2
IEEE/IEC
DS100267-7
August 1998
54AC109
•
54ACT109
Dual
JK
Positive
Edge-T
riggered
Flip-Flop
© 1998 National Semiconductor Corporation DS100267 www.national.com