SN54AC00, SN74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES


SCAS524C – AUGUST 1995 – REVISED SEPTEMBER 1996
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C0068 EPIC  (Enhanced-Performance Implanted
CMOS) 1-m m Process
C0068 Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), DIP
(N) Packages, Ceramic Chip Carriers (FK),
Flat (W), and DIP (J) Packages

description
The ‘AC00 contain four independent 2-input NAND
gates. Each gate performs the Boolean function of
Y = A C0083 B or Y = A + B in positive logic.
The SN54AC00 is characterized for operation over
the full military temperature range of –55°C to 125°C.
The SN74AC00 is characterized for operation from
–40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B
Y
H H L
L XH
X L H
logic symbol
†
11
8
6
3
4B
4A
3B
3A
2B
2A
1B
1A
4Y
3Y
2Y
1Y
13
12
10
9
5
4
2
1
&
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
logic diagram (positive logic)
Y
B
A
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
SN54AC00 . . . FK PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B 1A NC
3Y 3A
V 4B
2Y
GND
NC
CC
NC – No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
SN54AC00 ...J OR W PACKAGE
SN74AC00 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1996, Texas Instruments Incorporated