TL/F/6526
5474/DM5474/DM7474
Dual
Positive-Edge-Triggered
D
Flip-Flops
with
Preset,
Clear
and
Complementary
Outputs
June 1989
5474/DM5474/DM7474
Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs. The informa-
tion on the D input is accepted by the flip-flops on the posi-
tive going edge of the clock pulse. The triggering occurs at a
voltage level and is not directly related to the transition time
of the rising edge of the clock. The data on the D input may
be changed while the clock is low or high without affecting
the outputs as long as the data setup and hold times are not
violated. A low logic level on the preset or clear inputs will
set or reset the outputs regardless of the logic levels of the
other inputs.
Features
Y
Alternate Military/Aerospace device (5474) is available.
Contact a National Semiconductor Sales Office/Distrib-
utor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6526–1
Order Number 5474DMQB, 5474FMQB, DM5474J, DM5474W, DM7474M or DM7474N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
Inputs Outputs
PR CLR CLK D Q Q
LH XXHL
HL LH
LL XXH**
HHuHH L
LL H
HH LXQ
0
Q
0
HeHigh Logic Level
X e Either Low or High Logic Level
L e Low Logic Level
u
e Positive-going transition of the clock.
* e This configuration is nonstable; that is, it will not persist when either the preset and/or clear
inputs return to their inactive (high) level.
Q
0
e The output logic level of Q before the indicated input conditions were established.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.