Features
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5270 REV 1 12/22/98
BLOCK DIAGRAM
a73 Full militarized QED RM5270 microprocessor
a73 Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
a71 133, 150, 200 MHz operating frequencies – Consult Factory for
latest speeds
a71 260 Dhrystone2.1 MIPS
a71 SPECInt95 5.0, SPECfp95 5.3
a73 High performance system interface compatible with RM5260,
R4600, R4700 and R5000
a71 64-bit multiplexed system address/data bus for optimum price/
performance with up to 100 MHz operating frequency
a71 High performance write protocols maximize uncached write
bandwidth
a71 Supports clock divisors (2, 3, 4, 5, 6, 7, 8)
a71 5V compatible I/O’s
a71 IEEE 1149.1 JTAG boundary scan
a73 Integrated on-chip caches
a71 16KB instruction - 2 way set associative
a71 16KB data - 2 way set associative
a71 Virtually indexed, physically tagged
a71 Write-back and write-through on per page basis
a71 Pipeline restart on first double for data cache misses
a73 Integrated memory management unit
a71 Fully associative joint TLB (shared by I and D translations)
a71 48 dual entries map 96 pages
a71 Variable page size (4KB to 16MB in 4x increments)
a73 Integrated secondary cache controller (R5000 compatible)
a71 Supports 512K or 2MByte block write-through secondary
a73 High-performance floating point unit
a71 Single cycle repeat rate for common single precision operations
and some double precision operations
a71 Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
a71 Single cycle repeat rate for single precision combined multiply-
add operation
a73 MIPS IV instruction set
a71 Floating point multiply-add instruction increases performance in
signal processing and graphics applications
a71 Conditional moves to reduce branch frequency
a71 Index address modes (register + register)
a73 Embedded application enhancements
a71 Specialized DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
a71 I and D cache locking by set
a71 Optional dedicated exception vector for interrupts
a73 Fully static CMOS design with power down logic
a71 Standby reduced power mode with WAIT instruction
a71 6 Watts typical at 3.3V 200 MHz
a73 208-lead CQFP, cavity-up package (F17)
a73 208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
a73 179-pin PGA package (Future Product) (P10)
Preliminary
64-Bit Superscaler Microprocessor
ACT5270