42S32200
器件描述：512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
器件厂商：ISSI [Integrated Silicon Solution, Inc]
厂商主页：http://www.issi.com/
文件大小：982.93KB，共55页
Sponsor by e络盟器件资料摘要：
Integrated Silicon Solution, Inc. — 1-800-379-4774 1
PRELIMINARY INFORMATION Rev. 00B
08/14/03
IS42S32200 ISSI
®
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• Clock frequency: 166, 143 MHz
Fully synchronous; all signals referenced to a
positive clock edge
Internal bank for hiding row access/precharge
Single 3.3V power supply
LVTTL interface
Programmable burst length
– (1, 2, 4, 8, full page)
Programmable burst sequence:
Sequential/Interleave
Self refresh modes
4096 refresh cycles every 64 ms
Random column address every clock cycle
Programmable CAS latency (2, 3 clocks)
Burst read/write and burst read/single write
operations capability
Burst termination by burst stop and precharge
command
Industrial temperature availability
Package 400-mil 86-pin TSOP II
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42S32200 is organized
as 524,288 bits x 32-bit x 4-bank for improved performance.
The synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
512K Bits x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
PRELIMINARY INFORMATION
August 2003
PIN CONFIGURATION
(86-Pin TSOP (Type II)
VCC
I/O0
VCCQ
I/O1
I/O2
GNDQ
I/O3
I/O4
VCCQ
I/O5
I/O6
GNDQ
I/O7
NC
VCC
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VCC
NC
I/O16
GNDQ
I/O17
I/O18
VCCQ
I/O19
I/O20
GNDQ
I/O21
I/O22
VCCQ
I/O23
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
GND
I/O15
GNDQ
I/O14
I/O13
VCCQ
I/O12
I/O11
GNDQ
I/O10
I/O9
VCCQ
I/O8
NC
GND
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
GND
NC
I/O31
VCCQ
I/O30
I/O29
GNDQ
I/O28
I/O27
VCCQ
I/O26
I/O25
GNDQ
I/O24
GND
PIN DESCRIPTIONS
A0-A10 Address Input
BA0, BA1 Bank Select Address
I/O0 to I/O31 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
WE Write Enable
DQM0 to DQM3 Input/Output Mask
Vcc Power
GND Ground
VccQ Power Supply for I/O Pin
GNDQ Ground for I/O Pin
NC No Connection
PRELIMINARY INFORMATION Rev. 00B
08/14/03
IS42S32200 ISSI
®
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• Clock frequency: 166, 143 MHz
Fully synchronous; all signals referenced to a
positive clock edge
Internal bank for hiding row access/precharge
Single 3.3V power supply
LVTTL interface
Programmable burst length
– (1, 2, 4, 8, full page)
Programmable burst sequence:
Sequential/Interleave
Self refresh modes
4096 refresh cycles every 64 ms
Random column address every clock cycle
Programmable CAS latency (2, 3 clocks)
Burst read/write and burst read/single write
operations capability
Burst termination by burst stop and precharge
command
Industrial temperature availability
Package 400-mil 86-pin TSOP II
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42S32200 is organized
as 524,288 bits x 32-bit x 4-bank for improved performance.
The synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
512K Bits x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
PRELIMINARY INFORMATION
August 2003
PIN CONFIGURATION
(86-Pin TSOP (Type II)
VCC
I/O0
VCCQ
I/O1
I/O2
GNDQ
I/O3
I/O4
VCCQ
I/O5
I/O6
GNDQ
I/O7
NC
VCC
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VCC
NC
I/O16
GNDQ
I/O17
I/O18
VCCQ
I/O19
I/O20
GNDQ
I/O21
I/O22
VCCQ
I/O23
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
GND
I/O15
GNDQ
I/O14
I/O13
VCCQ
I/O12
I/O11
GNDQ
I/O10
I/O9
VCCQ
I/O8
NC
GND
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
GND
NC
I/O31
VCCQ
I/O30
I/O29
GNDQ
I/O28
I/O27
VCCQ
I/O26
I/O25
GNDQ
I/O24
GND
PIN DESCRIPTIONS
A0-A10 Address Input
BA0, BA1 Bank Select Address
I/O0 to I/O31 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
WE Write Enable
DQM0 to DQM3 Input/Output Mask
Vcc Power
GND Ground
VccQ Power Supply for I/O Pin
GNDQ Ground for I/O Pin
NC No Connection