 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1 Publication Order Number:
MC14066B/D
C0077C0067C0049C0052C0048C0054C0054C0066
C0081C0117C0097C0100 C0065C0110C0097C0108C0111C0103 C0083C0119C0105C0116C0099C0104C0047C0081C0117C0097C0100
C0077C0117C0108C0116C0105C0112C0108C0101C0120C0101C0114
The MC14066B consists of four independent switches capable of
controlling either digital or analog signals. This quad bilateral switch
is useful in signal gating, chopper, modulator, demodulator and
CMOS logic implementation.
The MC14066B is designed to be pin–for–pin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings
as large as the full supply voltage can be controlled via each
independent control input.
• Triple Diode Protection on All Control Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linearized Transfer Characteristics
• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical
• Pin–for–Pin Replacement for CD4016, CD4016, MC14016B
• For Lower R
ON
, Use The HC4066 High–Speed CMOS Device
MAXIMUM RATINGS (Voltages Referenced to V
SS
) (Note 2.)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5 V
I
in
Input Current (DC or Transient)
per Control Pin
±10 mA
I
SW
Switch Through Current ±25 mA
P
D
Power Dissipation,
per Package (Note 3.)
500 mW
T
A
Ambient Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature
(8–Second Soldering)
260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C0095C From 65C0095C To 125C0095C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
C0118 (V
in
or V
out
) C0118 V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14066BCP PDIP–14 2000/Box
MC14066BD SOIC–14 55/Rail
MC14066BDR2 SOIC–14 2500/Tape & Reel
MC14066BDT TSSOP–14
MC14066BF SOEIAJ–14
96/Rail
See Note 1.
MARKING
DIAGRAMS
1
14
PDIP–14
P SUFFIX
CASE 646
MC14066BCP
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
TSSOP–14
DT SUFFIX
CASE 948G
1
14
14066B
AWLYWW
14
066B
ALYW
1
14
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC14066B
AWLYWW
MC14066BFEL SOEIAJ–14 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MC14066BDTR2 TSSOP–14 2500/Tape & Reel
MC14066BDTEL TSSOP–14 2000/Tape & Reel