TL/F/5958
CD4027BM/CD4027BC
Dual
J-K
Master/Slave
Flip-Flop
with
Set
and
Reset
February 1988
CD4027BM/CD4027BC Dual J-K Master/Slave
Flip-Flop with Set and Reset
General Description
These dual J-K flip-flops are monolithic complementary
MOS (CMOS) integrated circuits constructed with N- and P-
channel enhancement mode transistors. Each flip-flop has
independent J, K, set, reset, and clock inputs and buffered
Q and Q outputs. These flip-flops are edge sensitive to the
clock input and change state on the positive-going transition
of the clock pulses. Set or reset is independent of the clock
and is accomplished by a high level on the respective input.
All inputs are protected against damage due to static dis-
charge by diode clamps to V
DD
and V
SS
.
Features
Y
Wide supply voltage range 3.0V to 15V
Y
High noise immunity 0.45 V
DD
(typ.)
Y
Low power TTL Fan out of 2 driving 74L
compatibility or 1 driving 74LS
Y
Low power 50 nW (typ.)
Y
Medium speed operation 12 MHz (typ.)
with 10V supply
Schematic and Connection Diagrams
TL/F/5958–1
Dual-In-Line Package
TL/F/5958–2
Top View
Order Number CD4027B
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.