3D3215
Doc #01014 DATA DELAY DEVICES, INC. 1
12/3/01 3 Mt. Prospect Ave. Clifton, NJ 07013
MONOLITHIC 5-TAP 3.3V
FIXED DELAY LINE
(SERIES 3D3215)
FEATURES PACKAGES
• All-silicon, low-power 3.3V CMOS technology
• Vapor phase, IR and wave solderable
• Auto- insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: 1.5ns through 300ns
• Total delay tolerance: 2% or 0.5ns (3.3V, 25C)
• Temperature stability: ±1% typical (0C-70C)
• Vdd stability: ±1% typical (3.0V-3.6V)
• Static Idd: 1.3ma typical
• Minimum input pulse width: 25% of total delay
FUNCTIONAL DESCRIPTION
The 3D3215 5-Tap Delay Line product family consists of fixed-delay
3.3V CMOS integrated circuits. Each package contains a single delay
line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-
tap (incremental) delay values can range from 1.5ns through 60ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D3215 is 3.3V CMOS-
compatible and features both rising- and falling-edge accuracy.
The all-CMOS 3D3215 integrated circuit has been designed as a
reliable, economic alternative to hybrid fixed delay lines. It is offered in a
standard 8-pin auto- insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
DASH # DELAY SPECIFICATIONS INPUT RESTRICTIONS
RECOMMENDED ABSOLUTE3D3215Z-xx
3D3215M-xx
TOTAL
DELAY (ns)
TAP-TAP
DELAY (ns) Max Freq Min P.W. Max Freq Min P.W.
-1.5 6.0 ± 0.5* 1.5 ± 0.7 23.8 MHz 21.0 ns 83.3 MHz 6.00 ns
-2 8.0 ± 0.5* 2.0 ± 0.8 20.8 MHz 24.0 ns 83.3 MHz 6.00 ns
-2.5 10.0 ± 0.5* 2.5 ± 1.0 18.5 MHz 27.0 ns 66.7 MHz 7.50 ns
-3 12.0 ± 0.5* 3.0 ± 1.3 16.7 MHz 30.0 ns 55.6 MHz 9.00 ns
-4 16.0 ± 0.5* 4.0 ± 1.3 13.9 MHz 36.0 ns 50.0 MHz 10.00 ns
-5 20.0 ± 0.5* 5.0 ± 1.4 11.9 MHz 42.0 ns 40.0 MHz 12.50 ns
-6 24.0 ± 0.5* 6.0 ± 1.4 10.4 MHz 48.0 ns 55.6 MHz 9.00 ns
-8 40.0 ± 0.8 8.0 ± 1.4 8.33 MHz 60.0 ns 41.7 MHz 12.00 ns
-10 50.0 ± 1.0 10.0 ± 1.5 6.67 MHz 75.0 ns 40.0 MHz 12.50 ns
-12 60.0 ± 1.2 12.0 ± 1.5 5.56 MHz 90.0 ns 33.3 MHz 15.00 ns
-15 75.0 ± 1.5 15.0 ± 1.5 4.42 MHz 113 ns 26.7 MHz 18.75 ns
-20 100 ± 2.0 20.0 ± 2.0 3.33 MHz 150 ns 20.0 MHz 25.00 ns
-25 125 ± 2.5 25.0 ± 2.5 2.66 MHz 188 ns 16.0 MHz 31.25 ns
-30 150 ± 3.0 30.0 ± 3.0 2.22 MHz 225 ns 13.3 MHz 37.50 ns
-40 200 ± 4.0 40.0 ± 4.0 1.67 MHz 300 ns 10.0 MHz 50.00 ns
-50 250 ± 5.0 50.0 ± 5.0 1.33 MHz 375 ns 8.0 MHz 62.50 ns
-60 300 ± 6.0 60.0 ± 6.0 1.11 MHz 450 ns 6.7 MHz 75.00 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns ± 1.5ns
NOTE: Any dash number between 1.5 and 60 not shown is also available as standard 2001 Data Delay Devices
datadelay
devices, inc.

3
8
7
6
5
1
2
3
4
IN
O2
O4
GND
VDD
O1
O3
O5
3D3215M-xx
DIP (300 Mil)
1
2
3
4
8
7
6
5
IN
O2
O4
GND
VDD
O1
O3
O5
3D3215Z-xx
SOIC (150 Mil)
PIN DESCRIPTIONS
IN Delay Line Input
O1 Tap 1 Output (20%)
O2 Tap 2 Output (40%)
O3 Tap 3 Output (60%)
O4 Tap 4 Output (80%)
O5 Tap 5 Output (100%)
VDD +3.3 Volts
GND Ground
N/C No Connection
For mechanical dimensions, click here .
For package marking details, click here .