October 1987
Revised January 1999
MM74C00
• MM74C02
•

MM
7
4
C04 Quad
2-I
nput
NAND Gat
e
•
Quad 2
-
I
nput
NO
R
Gate
• He
x I
n
ver
t
e
r
© 1999 Fairchild Semiconductor Corporation DS005877.prf www.fairchildsemi.com
MM74C00 • MM74C02 • MM74C04
Quad 2-Input NAND Gate •
Quad 2-Input NOR Gate •
Hex Inverter
General Description
The MM74C00, MM74C02, and MM74C04 logic gates
employ complementary MOS (CMOS) to achieve wide
power supply operating range, low power consumption,
high noise immunity and symmetric controlled rise and fall
times. With features such as this the 74C logic family is
close to ideal for use in digital systems. Function and pin
out compatibility with series 74 devices minimizes design
time for those designers already familiar with the standard
74 logic family.
All inputs are protected from damage due to static dis-
charge by diode clamps to V
CC
and GND.
Features
a73 Wide supply voltage range: 3V to 15V
a73 Guaranteed noise margin: 1V
a73 High noise immunity: 0.45 V
CC
(typ.)
a73 Low power consumption: 10 nW/package (typ.)
a73 Low power: TTL compatibility:
Fan out of 2 driving 74L

Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP and SOIC
MM74C00
Top View
MM74C02
Top View
MM74C04
Top View
Order Number Package Number Package Description
MM74C00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C02N M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide